This invention relates to channel status management for multichannel audio distribution.
The Audio Engineering Society and the European Broadcasting Union have established a standard which describes a signal format for distributing two channels of audio material in a digital data stream. The data stream, which is frequently referred to as the AES3 data stream, is composed of frames, and each frame of the AES3 data stream is composed of two channel subframes, which are referred to as subframe A and subframe B, in sequence. The format of one subframe is shown schematically in FIG. 1.
Referring to FIG. 1, each subframe of the AES3 data stream has 32 bits and includes a preamble occupying four bit times, 24 bits of payload data, and four control bits (V, U, C and P). The payload data consists of 20 bits of audio data and four bits of auxiliary data, which may be audio data. The audio data bits (20 or 24) represent one audio sample. Conventionally, the sample frequency of each channel of the AES3 data stream is in the range from 32 kHz to 50 kHz for most applications. For professional applications, the standard sample frequency is currently 48 kHz but there is a trend towards using a sample frequency of 96 kHz.
The AES3 data stream utilizes a biphase mark coded signal. In biphase mark coding, one source data bit occupies a single time slot. Each source data bit is represented by a two cell doublet. Each coding doublet begins, and therefore also ends, with a transition. A source data bit 1 generates a transition between the two cells of the doublet, whereas a source data bit zero does not. Thus, a source data bit zero is represented either as the doublet 00 or the doublet 11, while the source data bit 1 is represented either by the doublet 10 or the doublet 01. Because of the requirement that each coding doublet should end with a transition, the cell sequence 000 or 111 cannot be generated by encoding source data bits. In accordance with the AES3 standard, the first four time slots of each subframe constitute a preamble containing at least one occurrence of the three cell sequence 000 or 111. This brief departure from the usual biphase mark coding rules is known as a code violation.
There are three forms of preamble. The Z preamble designates the start of subframe A of a frame that is the first frame in a sequence of 192 frames, the A preamble designates the start of subframe A of other frames, and the B preamble designates the start of subframe B.
The upper waveform in FIG. 2 shows by way of example the pattern of cell values of the AES3 data stream during the interval about the boundary between subframe B of frame Nxe2x88x921 and subframe A of frame N whereas the lower waveform shows the corresponding pattern of NRZ data values. The last four bits of frame Nxe2x88x921 are the V, U, C and P bits and the first four bit times of frame N are occupied by the preamble. In the case of FIG. 2, the preamble is in one of two possible forms of the Z preamble. The preamble is followed by the four bits of auxiliary data: FIG. 2 illustrates the sequence 0, 1, 0, 1.
The sequence of 192 C (channel status) bits in channel A or channel B between two consecutive occurrences of the Z preamble constitutes a channel status block that conveys information regarding the type of data used to create that particular channel of the AES3 data stream. Since the Z preamble can occur only at the start of subframe A, the AES3 standard requires that the boundary of the channel status block for channel B should coincide with the boundary of the channel status block for channel A.
The AES3 standard requires that equipment that processes audio data and reinitializes the channel status bits must maintain the channel pair correlation and must re-stripe the Z framing so that the new channel status information can be recovered.
Frequently, the two channels of an AES3 data stream are related, for example as L+R and Lxe2x88x92R stereo channels, in which case the two channels will generally be processed in parallel and will not be subject to differential delay. Further, it will not generally be necessary or desirable to combine one channel of a pair of related channels with an unrelated channel. However, the AES3 standard does not require that the two channels of an AES3 data stream be related, and the possibility exists of its being desirable to construct an output data stream by extracting one channel from a first input AES3 data stream and combining it with one channel of a second input AES3 data stream. An impediment to constructing an output data stream in this way has been that the channel status blocks of the two input data streams would generally not be aligned and accordingly the new data stream would not comply with the AES3 standard.
U.S. patent application Ser. No. 09/436,461 filed Nov. 8, 1999, the entire disclosure of which is hereby incorporated by reference herein, discloses apparatus for multiplexing AES3 data streams to form a multichannel data distribution stream. In accordance with one part of the disclosure of that application, each subframe of the AES3 frame is truncated. The multichannel distribution frame has a header which includes a 4-bit preamble for multiplexer framing, and this allows the preamble of the individual AES3 subframes to be truncated to a single Z bit having the value 1 in the event that the preamble of subframe A is the Z preamble and a value 0 in the event that the preamble of subframe A is the A preamble.
In some circumstances, it may be desirable to extract two channels of the multichannel distribution frame and combine them to generate an AES3 data stream. Normally, it cannot be ensured that the boundaries of the channel status blocks of the two channels coincide.
Under the AES3 standard, the user bit U may be used in any way required by the user but the standard recognizes that it may be advantageous to adopt a block structure similar to that of the channel status bits, with block boundaries aligned with those of the channel status data blocks.
According to a first aspect of the present invention there is provided a method of processing first and second successions of data words, each data word including multiple payload data bits, a data block bit (C) and a block character (SOB) having a first state to indicate start of a sequence of data block bits and otherwise having a second state, said a method comprising detecting as a first event occurrence of the block character of the first succession of data words in the first state and as a second event the next succeeding occurrence of the block character of the second succession of data words in the first state, wherein the second event is delayed by a time Tz relative to the first event, reading the data block bits from successive data words of the first succession and generating a succession of delayed data block bits of the first succession of data words, delayed by said time Tz relative to the payload data bits of the first succession of data words, and inserting the data block bits of the delayed succession of data block bits in successive words of the first succession of data words, so that the start of the sequence of data block bits in the first succession of data words coincides with the start of the sequence of data block bits in the second succession of data words.
According to a second aspect of the present invention there is provided a routing switch for connection to a plurality of signal sources each providing a data stream composed of a succession of frames, each frame having first and second subframes, wherein the first subframe includes framing bits and each subframe includes multiple payload data bits and a data block bit, the framing bits having a first state to indicate start of a sequence of data block bits and otherwise having a second state, the succession of first subframes constituting a first channel and the succession of second subframes constituting a second channel, and the routing switch including a plurality of input modules having respective input terminals for connection to the signal sources, a plurality of output modules each having an output terminal for connection to a signal destination, and a routing core for supplying selectively a channel of a first data stream and a channel of a second data stream to any selected output module for combination to provide the output data stream, and wherein each output module includes a circuit which selectively delays the data block bits of one channel to bring the data block bits of the one channel into phase alignment with the data block bits of the other channel.
According to a third aspect of the present invention there is provided a method of processing first and second data streams each composed of a succession of frames, each frame having first and second subframes, the succession of first subframes constituting a first channel and the succession of second subframes constituting a second channel, wherein each subframe includes multiple payload data bits and a data block bit and the first subframe includes a framing character having a first state to indicate start of a sequence of data block bits and otherwise having a second state, said method comprising (a) composing an output data stream from a channel of the first data stream and a channel of the second data stream, and (b) delaying the data block bits of one channel relative to the payload data bits of the one channel to bring the data block bits of the one channel into phase alignment with the data block bits of the other channel.